1. Field of the Invention
The present invention relates to a design data processing method in a semiconductor device, more particularly to a design data processing method capable of shortening OPC processing time and increasing a process margin, a program of the method, and a manufacturing method of a semiconductor device by use of a mask made in accordance with the processing method.
2. Description of the Related Art
In recent years, a semiconductor manufacturing technology has advanced remarkably, and a semiconductor device having a minimum working size of 0.09 μm is manufactured. Such miniaturization is realized by the rapid progress of micropattern forming technologies such as a mask process technology, photolithography technology and etching technology.
When a pattern size is sufficiently large, as a design pattern, a plane shape of an LSI pattern to be formed on a wafer is drawn as it is, a mask pattern which is prepared with fidelity to the design pattern, the mask pattern is transferred onto the wafer through an optical system, and an underlayer is etched, whereby it is possible to form the pattern substantially as designed on the wafer. However, as miniaturization of the pattern advances, it becomes difficult to form the pattern with fidelity in each process, and a problem occurs that the final finished size does not satisfy the design pattern. To solve these problems, means (hereinafter referred to as mask design processing) becomes very important which prepares the mask pattern that is different from the design pattern in consideration of a conversion difference between the processes so that the final finished size becomes equal to a design pattern size.
The mask data processing includes a processing method to change the mask pattern by use of graphic data processing, a design rule checker or the like. In recent years, there are optical proximity correction (OPC) processing to correct an optical proximity effect (OPE) and the like. When these types of processing are performed, the mask pattern is appropriately corrected so that the final finished size reaches a desired size.
In recent years, with the miniaturization of a device pattern, a k1 value (k1=W/(NA/λ), wherein W is the dimension of the design pattern, λ is the exposure wavelength of an exposure apparatus and NA is the numerical aperture of a lens for use in the exposure apparatus) in a photolithography process is increasingly reduced. As a result, the OPE tends to be further enhanced, and a load of OPC processing becomes very large. To achieve a high precision of the OPC processing, a mainstream is a model-based OPC technique which is provided with a optical lithography simulator capable of correctly predicting the OPE and which can calculate an appropriate correction value for each mask pattern.
In the model-based OPC, a method is very important which calculates the correction value of the mask pattern to maximize a process margin. The process margin in the lithography includes a focus margin and a dose margin. In a conventional method, under specific conditions, the correction value of the mask pattern has been calculated so that the maximum design margin can be obtained with respect to an allowable size specification of the design pattern. However, with the decrease in the k1 value, it becomes difficult to obtain the predetermined dose margin, if this means is adopted (see, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2001-013668).
Therefore, there has been a demand, not only for a higher precision of the model-based OPC, but also for realization of a design data processing method capable of matching a shape on a wafer with predetermined shape specifications, a program to make the method possible, and a manufacturing method of a semiconductor device by use of a mask based on the design data processing method.